1. Field of the Invention
The present invention relates generally to an information processing system and, more specifically, to a digital information processing system employing memory modules constructed in serial bus architecture.
2. Description of Related Art
Referring to FIG. 1, a traditional information processing system 10 usually includes a chipset (or a memory controller) 12 and first and second Rambus in-line modules (RIMM) 14, 16, respectively. The chipset 12 and the memory modules 14, 16 are connected to a data bus 18 that includes a plurality of data lines, a clock line 20, and a reference voltage line 22. One end of the data bus 18 is connected to the chipset 12 while the other end is connected to a termination voltage Vterm (e.g., 1.8V) through termination resistors RDATA (e.g., 28Ω), forming a termination circuit. One end of the reference voltage line 22 is connected to the chipset 12 while the other end is connected to a reference voltage Vref. The reference voltage Vref acts as a logical threshold reference voltage of Rambus signaling level (RSL).
One end of the clock line 20 is connected to a clock generator 24 while the other end is connected to the termination voltage Vterm through a resistor RCLK. The clock generator 24 outputs a bus clock signal of 300˜400 MHz to be used in the chipset 12 and the memory modules 14, 16. The clock line 20 is divided into first and second segments 20a, 20b, respectively, which are electrically connected to each other at a turnaround position 20c on the inside of the chipset 12. The segments 20a, 20b have the same length and electrical characteristics as the data bus 18. The first segment 20a transfers a clock signal CTM for data transmissions from the memory modules, 14, 16, to the chipset 12, during read operations. The second segment 20b transfers a clock signal CFM for write operations from the chipset 12 to the memory modules 14, 16.
In a conventional RIMM such as a Rambus DRAM module system that employs a serial bus architecture, high frequency operation is achieved because the clock signals CTM (clock-to-master) and CFM (clock-from-master) are synchronized in the serial bus architecture. The clock signal CTM is an interface signal used to transfer the RSL signals to channels while the clock signal CFM is an interface signal used to receive the RSL signals from channels.
Unfortunately, using the serial bus architecture, the clock signal deteriorates with the higher operation frequency because the clock line 20 and the data bus 18 are not the same length. More specifically, the length between the two ends of the clock line 20 is 4L (where L is a length unit), while the length between the two ends of the data bus 18 is half that of the clock line (or 2L). Therefore, the clock signal CFM travels twice as far as a data signal does along the data bus 18. The power level of the clock signal CFM is therefore degraded by a corresponding amount.
As shown in FIG. 2, the amplitude of clock signal CFM is diminished and becomes more susceptible to noise sources on the channel. Accordingly, as the distance between devices and the chipset increases, the jittering of the clock signal CFM increases correspondingly, causing discrepancies between timings of data input and output. Moreover, with higher operation frequencies, a memory device mounted on the second memory module 16 rather than on the first memory module 14 becomes incapable of conducting a read operation or a write operation. This is because long distance the clock signal must travel causes it to arrive at the memory device with an invalid signal level due to signal degradation.